Semiconductor device having localized charge balance structure and method

ABSTRACT

In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional application of co-pending U.S. patentapplication Ser. No. 14/032,454 filed on Sep. 20, 2013, which claims thebenefit of priority from U.S. Provisional Application No. 61/710,526,which was filed on Oct. 5, 2012, both of which are fully incorporatedherein.

BACKGROUND

The present invention relates, in general, to electronics and, moreparticularly, to methods of forming semiconductors and structurestherefore.

Metal-oxide semiconductor field effect transistors (MOSFETs) are acommon type of power switching device. A MOSFET device includes a sourceregion, a drain region, a channel region extending between the sourceand drain regions, and a gate structure provided adjacent to the channelregion. The gate structure includes a conductive gate electrode layerdisposed adjacent to and separated from the channel region by a thindielectric layer.

When a MOSFET device is in the on state, a voltage is applied to thegate structure to form a conduction channel region between the sourceand drain regions, which allows current to flow through the device. Inthe off state, any voltage applied to the gate structure is sufficientlylow so that a conduction channel does not form, and thus current flowdoes not occur. During the off state, the device must support a highvoltage between the source region and the drain region.

Today's higher voltage power switch market is driven by at least twomajor parameters, which include breakdown voltage (BVdss) and on-stateresistance (Rdson). For a specific application, a minimum breakdownvoltage is required, and in practice, designers typically can meet aBVdss specification. However, this is often at the expense of Rdson.This trade-off in performance is a major design challenge formanufacturers and users of high voltage power switching devices.

Recently, superjunction devices have gained in popularity to improve thetrade-off between Rdson and BVdss. In previous n-channel superjunctiondevices, multiple heavily-doped diffused n-type and p-type regionsreplace one lightly doped n-type epitaxial region. In the on state,current flows through the heavily doped n-type regions, which lowersRdson. In the off or blocking state, the heavily doped n-type and p-typeregions deplete into or compensate each other to provide a high BVdss.More recently, price points for superjunction devices have become moreattractive and market trends are driving demand for lower conduction andswitching losses. Additional factors driving demands for superjunctiondevices include increased power conversion efficiency, increased powerdensity requirements, smaller package requirements with demand forbetter performance, adoption of surface mount packages, and reductionsin heat sinking requirements.

Although superjunction devices look promising, significant challengesstill exist in manufacturing them. Another problem with previoussuperjunction devices is that the energy capability (Eas) underunclamped inductive switching (UIS) testing is often too low underoptimum charge balance (for example, charge balance (CB) approaching 0%)or within a desired charge balance window. Such inadequate Eascapability is believed to be from low snapback current (Isnapback) inthe reverse blocking IdVd curve. A low Isnapback can produce a pureelectrical failure observed at few nanoseconds after switching-off thedevice in the typical UIS test. The electrical failure can occur when anegative differential resistance is reached at a certain region of theactive area, thus producing a non-uniform current distribution and,eventually, a current focalization or a “hot spot”. Additionally, a lowIsnapback can limit the energy capability under other tests, such asreverse recovery tests.

Accordingly, it is desirable to have a structure for and method ofmaking a superjunction semiconductor device that improves UISperformance. It would be beneficial if the structure and methodmaintained the design trade-offs between UIS, Rdson, and BVdss.Additionally, it would beneficial if the structure and method did notadd significant process complexity or excessive costs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a partial cross-sectional view of a semiconductordevice in accordance with an embodiment of the present invention;

FIG. 2 illustrates graphical information of reverse current-voltage (I-Vor IV) characteristics comparing a semiconductor device in accordancewith the present invention with a prior structure; and

FIG. 3 illustrates an embodiment of a process flow for manufacturing asemiconductor device in accordance with the present invention.

For simplicity and clarity of the illustration, elements in the figuresare not necessarily drawn to scale, and the same reference numbers indifferent figures denote the same elements. Additionally, descriptionsand details of well-known steps and elements are omitted for simplicityof the description. For clarity of the drawings, certain regions ofdevice structures, such as doped regions or dielectric regions, may beillustrated as having generally straight line edges and precise angularcorners. However, those skilled in the art understand that, due to thediffusion and activation of dopants or formation of layers, the edges ofsuch regions generally may not be straight lines and that the cornersmay not be precise angles.

Furthermore, the term “major surface” when used in conjunction with asemiconductor region, wafer, or substrate means the surface of thesemiconductor region, wafer, or substrate that forms an interface withanother material, such as a dielectric, an insulator, a conductor, or apolycrystalline semiconductor. The major surface can have a topographythat changes in the x, y and z directions.

DETAILED DESCRIPTION OF THE DRAWINGS

Certain previous superjunction technologies are based on a local chargebalanced (LCB) concept. By way of example, in LCB devices superjunctiontrenches can be formed by reactive ion etching in the active area of asemiconductor substrate and then lined with as-formed heavily-dopedn-type and p-type layers. In one embodiment, an n-type layer is formedfirst, and then a p-type layer is formed thereafter. Typically, both then-type and p-type doping is uniform along the entire superjunctiontrench depth. Thus, because there is no imbalance along thesuperjunction trench depth the electric field is therefore uniform foroptimum charge balance and highest breakdown voltage. However, thisconfiguration has been found to be underperforming for UIS conditions(where high avalanche current densities can occur) because of what istermed the Egawa effect. UIS performance data for previous 650 volt LCBdevices has shown that for a charge balance (CB) of 0%, breakdownvoltage (BVdss) ranges from about 650 volts (V) to about 750V, but UISranges from close to zero (0) milli-Joules/cm² (mJ/cm²) to just above650 mJ/cm², which is below desired target specifications. This dataillustrates that an undesirable UIS performance can occur around anoptimum charge balance condition where maximum breakdown can occur.Specifically, for an optimum charge balance and maximum breakdownvoltage, the UIS robustness is near zero. This illustrates the problemto be addressed by the present embodiments that utilize a sufficientlytailored charge balanced structure in order to enhance UIS performanceto be more acceptable.

The present description discloses a configuration that improves UISperformance, for example, in LCB superjunction structures. In thepresent description, the configuration is described in tworepresentative embodiments both configured to create an imbalancedsuperjunction structure across a selected CB window. Stated another way,the present embodiments are configured to unbalance the dopant profilesin a selected location(s) in or proximate to the superjunction structureor column(s) so as to modify the electric field distribution along thesuperjunction column. The modified electric field has a less than flatprofile or has a less than uniform profile along the superjunctioncolumn over the selected CB window. The present embodiments areconfigured to address the UIS robustness issues observed in previoussuperjunction embodiments.

The two example embodiments include electric field tailoring using ionimplantation or a connection implant into upper portions of thesuperjunction structures, and electric field tailoring by usingintrinsic-epitaxial (i-epi) dopant profile tailoring adjacent to thesuperjunction structures. Both embodiments are based, at least in part,on electric field (E-field) engineering such that the resultant E-fieldalong the superjunction trench is purposely imbalanced. As a result,when minority and majority carriers are flowing in the device underavalanche conditions, minority and majority carriers do notsignificantly alter the E-field in such a way that the E-field becomescompletely flat (as in an optimum charge balanced condition in previousdevices). A flat E-field is believed to lead to the Egawa effect (alsotermed “E-field quenching”), which can lead to early destruction of thedevice due to current crowding effects.

In accordance with the present embodiments, the induced non-uniformelectric field can allow the voltage (that is, the area under theelectric field distribution) to increase when the drift region isflooded with excess majority and minority carriers under avalancheconditions (for example, during a UIS test). Hence, the I-Vcharacteristics of the present embodiments exhibit positive differentialresistance (PDR), balancing the current—in contrast to negativedifferential resistance (NDR) found in previous devices, which can causefilamentation and destruction. The current level at which the NDR setsin is called the snapback current (Isnapback). The present embodimentsas described subsequently are configured to increase the snapbackcurrent by, for example, delaying the NDR in the reverse I-Vcharacteristic. Although the following embodiments are described as ann-channel device, those skilled in the art will appreciate that thepresent embodiments are suitable for p-channel devices by reversing thedescribed conductivity types or for complementary configurations.

FIG. 1 shows a partial cross-sectional view of an insulated gate fieldeffect transistor (IGFET), MOSFET, LCB superjunction device,superjunction structure, charged-compensated, LCB structure, orswitching device or cell 10 in accordance with a first embodiment thatis configured to address the issues with prior devices describedpreviously as well as others. By way of example, device 10 is among manysuch devices integrated with logic and/or other components into asemiconductor chip as part of a power integrated circuit. Alternatively,device 10 is among many such devices integrated together to form adiscrete transistor device.

Device 10 includes a region of semiconductor material 11, whichcomprises for example, an n-type silicon substrate 12 having aresistivity in a range of approximately 0.001 to about 0.01 ohm-cm, andmay be doped with arsenic or phosphorous. In the embodiment shown,substrate 12 provides a drain region for device 10, which is adjacent toa conductive layer 13. A semiconductor layer 14 is formed in, on, oroverlying substrate 12 and can be n-type and doped light enough in oneembodiment so as to not impact charge balance in the trench compensationregions described below. In one embodiment, layer 14 is formed usingepitaxial growth techniques. In an embodiment suitable for a 650 voltdevice, layer 14 is doped n-type with a dopant concentration of about1.0×10¹³ atoms/cm³ to about 5.0×10¹⁴ atoms/cm³, and has a thickness onthe order of about 40 microns to about 70 microns. Note that, althoughsemiconductor layer 14 is shown as thicker than substrate 12 in thedrawings, substrate 12 can be thicker. It is shown this way for ease ofunderstanding in the drawings. The thickness of layer 14 is increased ordecreased depending on the desired BVdss rating of device 10.Additionally, those skilled in the art will understand that an insulatedgate bipolar transistor (IGBT) device is achieved with the presentstructure by, for example, changing the conductivity type of substrate12 to p-type (i.e., opposite to semiconductor layer 14). In an optionalembodiment, substrate 12 may further include an n+ type buffer layerthat is formed prior to semiconductor layer 14.

Device 10 further includes spaced apart filled trenches, compensatingtrenches, semiconductor material filled trenches, charge-compensatedtrench regions, LCB regions, LCB structures, charge-compensated filledtrenches, compensation trenches, localized vertical charge compensationstructures, or LCB regions or pillars 22. As used herein, chargecompensation generally means that the total charge of the oppositeconductivity type layers is substantially or generally balanced orequal. Charge-compensated filled trenches 22 include a plurality oflayers or multiple pillars of material, conductive material orsemiconductor material 220, including at least two layers, structures,or pillars of opposite conductivity type (i.e., at least one each ofn-type and p-type), which may be separated by an intrinsic, buffer, orlightly doped semiconductor layer or layers. As shown in FIG. 1,material 220 includes a pillar or layer 221 of n-type semiconductormaterial adjoining semiconductor layer 14 along sidewall surfaces of thetrenches.

In accordance with a one embodiment, layers 221 are of the sameconductivity type as source regions 33, and form a primary vertical lowresistance current path from the channel to the drain when device 10 isin the on-state. A layer 222 of compensating p-type semiconductormaterial is formed overlying layer 221. By way of example, n-type layers221 and p-type layers 222 can have a dopant concentration on the orderof about 1.0×10¹⁵ atoms/cm³ to about 1.0×10¹⁷ atoms/cm³, and each canhave a thickness of about 0.1 microns to about 0.4 microns. Depending onthe desired charge balance, the foregoing dopant concentrations areincreased or decreased accordingly. When device 10 is in an off state,p-type layers 222 and n-type layers 221 compensate each other to providean increased BVdss characteristic. Although no intrinsic or bufferlayers are shown in the device of FIG. 1, it is understood that they maybe present in earlier steps in fabrication and may not be as evidentbecause dopant can diffuse into such layers during subsequent hightemperature processing. In one embodiment, layers of semiconductormaterial 220 comprise a single crystalline semiconductor material andhave as-formed dopant profiles.

In one embodiment, device 10 also includes one or more dielectric layersor a dielectric plug, or dielectric liner 28 formed overlying pillars220 within trenches 22. In one embodiment, dielectric layer 28 is adeposited silicon oxide layer. In one embodiment, dielectric layer 28can be multiple dielectric layers deposited or formed at different stepsand can be different materials. Although not shown, it is understoodthat during the formation of device 10, n-type dopant from highly dopedsubstrate 12 can diffuse into the lower portions of LCB trenches 22 sothat those portions of trenches 22 within substrate 12 become moreheavily doped n-type. When the optional n+ type buffer layer is used inconjunction with substrate 12, trenches 22 preferably extend into the n+type buffer layer.

In accordance with the present embodiment, device 10 further includesimbalanced regions, doped regions, p-connection regions, topp-connection regions, or implanted regions 223 formed proximate to, ator along upper portions of trenches 22. Doped regions 223 are configuredto make the top or upper portions of trenches 22 higher doped and in thecase of the present embodiment, more p-dopant rich or p-rich. In oneembodiment, a p-type (or n-type when device 10 is configured as ap-channel device) connection ion implant using a predetermined implantangle(s) to implant dopant into the superjunction trench area can beused to formed doped regions 223 to create a charge imbalance in LCBtrenches 22. In one embodiment, about the upper 5 to 15 microns of thedevice can be made more p-rich in the superjunction trench area. In oneembodiment, about the upper 10 microns of the device can be made morep-rich. In the present embodiment, an ion implant dose in a range fromabout 2.0×10¹² atoms/cm² to about 5.0×10¹³ atoms/cm² can be used. Inaccordance with a first embodiment, an angled top boron implant can beperformed into a charge balanced structure. The implant is such thatpart of the charge balanced structure is deliberately made more p-richcompared to previous structures to intentionally create a chargeimbalance.

Additionally, it was observed that the charge imbalance along thesuperjunction column can be adjusted using different implant angles toform doped regions 223. For example, in one embodiment using a 200 KeV,6.0×10¹² atoms/cm² dose and a 5 degree implant angle, the top 10 micronsof the superjunction column are approximately 25% p-rich. As a result,the electric field remains less than flat (optimum) over a 25% chargeimbalance window. In an alternative embodiment, the implant step can bedone in multiple twist angles. In one embodiment, the implant step canbe done with either two twist angles or four twist angles with a tiltangle of a few degrees.

Device 10 also includes a well, base, body or doped regions 31 formed insemiconductor layer 14 between and in proximity to, adjacent to, oradjoining LCB trenches 22. Body regions 31 can extend from major surface18 of semiconductor material 11. In one embodiment, body regions 31comprise p-type conductivity, and have a dopant concentration suitablefor forming an inversion layer that operates as conduction channels 45of device 10. Body regions 31 extend from major surface 18 to a depth ofabout 1.0 to about 5.0 microns. Those skilled in the art will appreciatethat body regions 31 can comprise a plurality of individually diffusedregions, or comprise a connected, single or commonly diffused region ofselected shape, or can comprise combinations thereof.

N-type source regions 33 are formed within, above, or in body regions 31and extend from major surface 18 to a depth of about 0.2 microns toabout 0.5 microns. In one embodiment, portions of major surface 18 canextend down and then outward from the edges of source regions 33 so thatcontact is made to horizontal and vertical surfaces of source regions 33by source contact layer 63. One or more p-type body contact regions 36are formed in at least a portion of each body region 31. Body contactregions 36 are configured to provide a lower contact resistance to bodyregion 31, and to lower the sheet resistance of body regions 31 undersource regions 33, which suppresses parasitic bipolar effects.

Device 10 further includes a trench gate or control structure 157adjoining body regions 31 and source regions 33. Control structure 157is laterally spaced apart from adjacent charge-compensated trench 22.That is, control structure 157 does not overlie charge-compensatedtrench 22. Trench gate structure 157 includes a gate trench 158 and agate dielectric layer 43 formed overlying surfaces of gate trench 158.In one embodiment, gate dielectric layer 43 comprises a silicon oxide,and has a thickness of about 0.05 microns to about 0.1 microns. Inanother embodiment, gate dielectric layer 43 has a thickness at thelower surfaces of gate trench 158 that is greater or thicker than thethickness of gate dielectric layer 43 along the sidewalls of gate trench158. In alternative embodiments, gate dielectric layer 43 comprisessilicon nitride, tantalum pentoxide, titanium dioxide, barium strontiumtitanate, or combinations thereof including combinations with siliconoxide, or the like.

Trench gate structure 157 further includes a conductive gate region 57formed within control or gate trench 158 and overlies gate dielectriclayer 43. In one embodiment, a source region 33 is interposed between aconductive gate region 57 and a charge compensation trench 22.Conductive gate region 57 comprises, for example, n-type polysilicon.Although conductive gate region 57 is shown as substantially co-planarwith major surface 18, conductive gate region 57 may extend higher orabove major surface 18 or may be recessed below major surface 18. Trenchgate structure 157 is configured to control the formation of channels 45and the conduction of current in device 10.

To facilitate a sub-surface current path, device 10 can further includen-type link, n-type doped layers or sub-surface doped layers 26.Specifically, doped layers 26 are configured to provide a sub-surfaceconduction path (i.e., horizontally-oriented conduction or current path)between the drain ends of channels 45 and n-type layers 221, which arethe primary conduction layers or vertical conduction or current paths inLCB trenches 22. That is, in device 10 current flows vertically throughchannels 45, then horizontally through doped layers 26, and thenvertically through layers 221. Doped layers 26 are configured so thatcurrent flow is isolated from major surface 18 by body regions 31 andbody contact regions 36, which are opposite conductivity types (p-type)from doped layers 26 (n-type).

Source contact layer 63 is formed overlying major surface 18 and makescontact to both source regions 33 and body contact regions 36. Althoughshown as a partial layer, it is understood that source contact layer 63can overlie major surface 18 and is isolated from gate electrode 57 byan interlayer dielectric structure (not shown). In one embodiment,source contact layer 63 comprises a titanium/titanium nitride barrierlayer and an aluminum silicon alloy formed overlying the barrier layer,or other materials known to those of skill in the art. Drain contactlayer 13 is formed overlying an opposing surface of semiconductormaterial 11, and comprises, for example, a solderable metal structuresuch as titanium-nickel-silver, chrome-nickel-gold, or the like.

The operation of device 10 proceeds as follows. Assume that sourceterminal 63 is operating at a potential V_(S) of zero volts, conductivegate regions 157 receive a control voltage V_(G)=5.0 volts, which isgreater than the conduction threshold of device 10, and drain terminal13 operates at drain potential V_(D)=5.0 volts. The values of V_(G) andV_(S) cause body region 31 to invert adjacent conductive gate regions157 to form vertical channels 45, which electrically connect sourceregions 33 to doped regions 26. A device current Id flows from drainterminal 13 and is routed through n-type pillars 221, doped layer 26,channels 45, source regions 33, to source terminal 63. Hence, current Idflows vertically through n-type pillars 221 to produce a lowon-resistance, and horizontally through n-type links 26 keeping thecurrent path isolated from major surface 18. In one embodiment, Id=1.0amperes. To switch device 10 to the off state, a control voltage V_(G)of less than the conduction threshold of the device is applied toconductive gate regions 157 (e.g., V_(G)<5.0 volts). This removeschannels 45 and Id no longer flows through device 10. In the off state,n-type pillars 221 and p-type pillars 222 compensate each other as thedepletion region from the primary blocking junction spreads, whichenhances BVdss.

FIG. 2 illustrates graphical information including breakdown voltage andsnapback current as a function of charge balance comparing device 10 ofthe present embodiment to a previous device. Curve 201 is breakdownvoltage for a prior device that does not have doped regions 223, curve202 is breakdown voltage for device 10 with doped regions 223, curve 203is snapback current for a prior device that does not have doped regions223, and curve 204 is snapback current for device 10 with doped regions223. In comparing curves 203 and 204 in FIG. 2, it is illustrated thatdoped regions 223 provide a charge imbalance that results in a reductionof NDR in the I-V characteristic, leading to higher snapback currents(lack of U-shape in Isnapback curve 204 compared to curve 203) hencebetter UIS capability. In one embodiment, the snapback current (onset ofNDR) improves by over 5 decades compared to previous devices.

In other embodiments, is was observed that a 3 degree implant angle(using, for example, an ion implant dose of 6.0×10¹² atoms/cm² at 200KeV) made approximately the top 20 microns of the superjunction columnapproximately 14% p-rich, a 7 degree implant angle made approximatelythe top 7 microns of the superjunction column approximately 33% p-rich,a 10 degree implant angle made approximately the top 5 microns of thesuperjunction column approximately 50% p-rich, and a 20 degree implantangle made approximately the top 3 microns of the superjunction columnapproximately 150% p-rich.

Additionally, UIS studies of device 10 showed that device 10 havingdoped regions 223 improved UIS robustness (for example, greater than 600milli Joules (mJ)) compared to prior devices that do not have dopedregions 223 (for example, approaching 0 mJ). Further, it was observedthat the breakdown voltage distribution of device 10 has a more narrowdistribution compared to previous devices that do not include dopedregions 223, which is believed to be due to the purposely induced fieldimbalance in accordance with the present embodiment.

FIG. 3 illustrates a process sequence to form doped regions 223 in aconnection implant in accordance with an embodiment of the presentinvention. In a first step 301, region of semiconductor material 11 isprovided with a hard mask formed on major surface 18. By way of example,the hard mask can be oxide-nitride-oxide configuration. Openings arethen formed in the hard mask layer to expose portions of major surface18 where trenches 22 will be formed.

In step 302, a trench etch is used to form trenches 22 extending frommajor surface 18 of region of semiconductor material 11. In oneembodiment, Deep Reactive Ion Etching (DRIE) etching with a fluorine orchlorine based chemistry can be used to form trenches 22. Severaltechniques are available for DRIE etching trenches 22 includingcryogenic, high-density plasma, or Bosch DRIE processing. In step 303, asuperjunction structure, such as LCB structure 220, can then be formedwithin trenches 22. In one embodiment, an intrinsic epi—n-typeepi—intrinsic epi—p-type epi—intrinsic epi pillar structure can beformed. In one embodiment, the superjunction structure is formed to becharge balanced. In step 304, a first dielectric liner can then beformed over the charge balanced structure. In one embodiment, an oxidecan be used. In step 305, a connection implant or p-type implant can bemade into the superjunction structure to form doped region 223 toconnect body region 31 to the p-type pillar 222 and to create the chargeimbalance of the present embodiment at a selected implant angle orangles as described previously. In step 306, a second dielectric linercan then be formed over the first dielectric liner to form dielectricstructure 28.

In another embodiment, charge imbalancing of the superjunction column222 can also be achieved by tailoring the doping profile ofsemiconductor layer 14 adjoining the superjunction trench 22, which canbe intrinsic epi or i-epi. In accordance with the second embodiment,semiconductor layer 14 is provided with a non-uniform dopant profile. Inone embodiment, semiconductor layer 14 is provided with a substantiallylinear graded dopant profile. In one embodiment, semiconductor layer 14has a dopant concentration of about 8.0×10¹³ atoms/cm³ proximate todoped layers 26 of device 10, and then linearly increased over thethickness of semiconductor layer 14 towards substrate 12 toapproximately 2.0×10¹⁵ atoms/cm³. This linear profile was observed toresult in a linear variation of the CB across the superjunction columnin trench 22 (for example, CB can vary over 40% across the SJ column).The resulting I-V characteristics of this embodiment showed no NDR up tovery high current levels (for example, greater than 50 amps). Inaccordance with the present embodiment, the configuration showed that alinearly graded n-epi provides a positive differential resistance acrossa selected charge balance window, which improves UIS performancecompared to prior superjunction devices. In a further embodiment, bothdoped regions 223 and the non-uniform dopant profile with semiconductorlayer 14 can be used.

In view of all of the above, it is evident that a novel method andstructure are disclosed. Included, among other features, isintentionally creating a charge imbalance in a LCB superjunctionstructure. In one embodiment, a doped region such as a p-type region isformed near an upper portion of the superjunction structure. In anotherembodiment, the semiconductor region adjacent to the superjunctionstructures has a non-uniform dopant profile with a lower dopantconcentration near the upper surface of the superjunction structure andthen increasing towards a lower portion of the superjunction structure.The resulting charge imbalance from the structure induces a non-uniformelectric field and can allow the voltage (that is, the area under theelectric field distribution) to increase when the drift region isflooded with excess majority and minority carriers under avalancheconditions (for example, during a UIS test) to improve performance.Hence, the I-V characteristic of the present embodiments exhibitpositive differential resistance (PDR), balancing the current—incontrast to NDR found in previous devices, which can cause filamentationand destruction.

While the subject matter of the invention is described with specificpreferred embodiments and example embodiments, the foregoing drawingsand descriptions thereof depict only typical embodiments of the subjectmatter, and are not therefore to be considered limiting of its scope. Itis evident that many alternatives and variations will be apparent tothose skilled in the art. For example, described dopant conductivitytypes can be reversed.

As the claims hereinafter reflect, inventive aspects may lie in lessthan all features of a single foregoing disclosed embodiment. Thus, thehereinafter expressed claims are hereby expressly incorporated into thisDetailed Description of the Drawings, with each claim standing on itsown as a separate embodiment of the invention. Furthermore, while someembodiments described herein include some but not other featuresincluded in other embodiments, combinations of features of differentembodiments are meant to be within the scope of the invention and meantto form different embodiments as would be understood by those skilled inthe art.

We claim: 1-14. (canceled)
 15. A method for forming a semiconductordevice structure comprising: providing a region of semiconductormaterial having a major surface; forming a superjunction structurewithin the region of semiconductor material that comprises pillars ofmaterial; and forming a doped structure adjoining at least a portion ofthe superjunction structure and configured to create a charge imbalancewithin the superjunction structure.
 16. The method of claim 15, whereinforming the doped structure comprises ion implanting a dopant into upperportions of the superjunction structure.
 17. The method of claim 16,wherein ion implanting the dopant comprises ion implanting the dopantusing at least one angle between about 0 degrees and 20 degrees, andwherein ion implanting the dopant comprises ion implanting boron at anion implant dose between about 6×10¹² atoms/cm² and about 5×10¹³atoms/cm².
 18. The method of claim 15, wherein forming the dopedstructure comprises forming an epitaxial layer having a non-uniformdopant profile as part of the region of semiconductor material, andwherein forming the superjunction structure comprises forming thesuperjunction structure within the epitaxial layer.
 19. The method ofclaim 18, wherein forming the epitaxial layer comprises forming theepitaxial layer with a linearly graded dopant profile.
 20. The method ofclaim 18, wherein forming the epitaxial layer comprises forming theepitaxial layer having a lower dopant concentration near an upperportion of the superjunction structure and having a higher dopantconcentration near a lower portion of the superjunction structure.
 21. Amethod for forming a semiconductor device structure comprising:providing a substrate having a first semiconductor layer overlying thesubstrate and having a major surface spaced apart from the substrate;forming a trench extending from the major surface into the semiconductorlayer, wherein the trench comprises a sidewall surface; forming a firstconductivity type region along the sidewall surface of the trench andhaving a generally vertical orientation; forming a second conductivitytype region adjacent to the first conductivity type region, wherein thefirst conductivity type region and the second conductivity type regionform a localized superjunction structure; and providing a first dopedregion of the second conductivity type proximate to the localizedsuperjunction structure and configured to create a charge imbalance inthe localized superjunction structure.
 22. The method of claim 21further comprising: forming a control electrode proximate to the majorsurface and spaced apart from the localized superjunction structure;forming a body region adjacent the major surface, the body region beinglaterally interposed between the control electrode and the localizedsuperjunction structure, wherein the localized superjunction structureadjoins a vertically oriented side surface of the body region and thefirst conductivity type semiconductor layer adjoins a bottom surface ofthe body region, and wherein the body region extends downward from themajor surface to a first depth.
 23. The method of claim 22, whereinproviding the first doped region comprises: providing the first dopedregion extending from the major surface to a top surface of the secondconductivity type region, wherein the first doped region has a higherdopant concentration than the second conductivity type region, andwherein: a first portion of the first doped region overlaps a topportion of the first conductivity type region to laterally connect thebody region to the second conductivity type region, the first portion ofthe first doped region abutting the vertically oriented side surface ofthe body region, the first doped region extends vertically downward fromthe major surface to a second depth greater than the first depth, andthe first conductivity type region separates a second portion of thefirst doped region from at least a portion of the vertically orientedside surface of the body region.
 24. The method of claim 22 furthercomprising: forming a second doped region in the semiconductor layerbelow the body region, the second doped region being configured toconnect a drain end of the channel region to the first conductivity typeregion.
 25. The method of claim 21, wherein providing the first dopedregion comprises ion implanting a dopant into upper portions of thelocalized superjunction structure.
 26. The method of claim 25, whereinion implanting the dopant comprises ion implanting the dopant using atleast one angle between about 0 degrees and 20 degrees, and wherein ionimplanting the dopant comprises ion implanting boron at an ion implantdose between about 6×10¹² atoms/cm² and about 5×10¹³ atoms/cm².
 27. Amethod for forming semiconductor device comprising: providing a regionof semiconductor material having a major surface; forming a trenchextending from the major surface into the region of semiconductormaterial, wherein the trench has a sidewall surface; providing asuperjunction structure in the trench and comprising a firstconductivity type region along the sidewall surface of the trench andhaving a generally vertical orientation, the superjunction structurefurther comprising a second conductivity type region adjacent to thefirst conductivity type region; providing a body region adjacent themajor surface and the superjunction structure, the body region beingconfigured to form a channel region, wherein the body region has avertically oriented side surface adjoining the trench; providing acontrol electrode, wherein the control electrode adjoins a portion ofthe body region; providing a source region adjacent the body region; andproviding a first doped structure extending from the major surface to atop surface of the second conductivity type region and configured tocreate a charge imbalance within an upper portion of the superjunctionstructure, wherein the first doped structure has a dopant concentrationhigher than the second conductivity type region.
 28. The method of claim27, wherein providing the first doped structure comprises; providing afirst portion of the first doped structure overlapping a top portion ofthe first conductivity type region and the sidewall surface of thetrench to laterally connect the body region to the second conductivitytype region, the first portion of the first doped region contacting thevertically oriented side surface of the body region, and providing asecond portion of the first doped structure laterally separated from atleast a portion of the vertically oriented side surface of the bodyregion by a portion of the first conductivity type region.
 29. Themethod of claim 27, further comprising: providing a second dopedstructure in the region of semiconductor material, wherein the seconddoped structure is disposed below the body region, the second dopedstructure being configured to connect a drain end of the channel regionto the superjunction structure.
 30. The method of claim 27, wherein:providing the region of semiconductor material comprises a providingsemiconductor substrate and a semiconductor layer on the semiconductorsubstrate; providing the superjunction structure comprises providinggenerally vertically oriented n-type and p-type semiconductor materialpillars within the semiconductor layer.
 31. The method of claim 27,wherein: providing the first doped structure comprises providing thefirst doped region extending from the major surface to a first depth;and providing the body region comprises providing the body regionextending from the major surface to a second depth less than the firstdepth.
 32. The method of claim 31, wherein the first depth is between 5microns and 15 microns.
 33. The method of claim 27, wherein providingthe first doped structure creates the charge imbalance between about 5%and about 10%.
 34. The method of claim 27, wherein providing the firstdoped region comprises: forming a first dielectric liner on thesuperjunction structure; ion implanting a dopant into upper portions ofthe superjunction structure; and forming a second dielectric liner onthe first dielectric liner.